- #WINALIGN 9.0 CD UPDATE#
- #WINALIGN 9.0 CD FULL#
Amiga Bootblock Reader brainfile support (copy ABR package xml files to \plugins\ABR). 
Uses DD+OFS if selected file fits (like previously), then DD+FFS, finally HD+FFS (if drive is HD).
Executable as a disk image mounting now supports FFS and HD disks. END+F5 = select CD image, END+SHIFT+F5 = eject CD. Added CD image select/eject keyboard shortcut. #WINALIGN 9.0 CD FULL#
All Z2 DMA HD controllers are now 24-bit addressing capable by default (real world capability), checkbox option added to enable full 32-bit capability (emulation only).bsdsocket.library SBTC_GET_BYTES_RECEIVED, SBTC_GET_BYTES_SENT, SIOCIFADDR, SIOCIFFLAGS, SIOCIFBRDADDR, SIOCIFCONF, SIOCIFNETMASK, SIOCIFMETRIC and SIOCIFMTU support added.
vice CMD_WRITE with io_Length=-1, EOFMODE and Mark and Space parity support implemented.Picasso96 v3.0+ uaegfx screen dragging and dual palette support.Configurable disassembly format, DMA debugger DDFSTRT, DDFSTOP, horizontal window, vertical window, blanking markers, full 32-bit/64-bit bitplane/sprite pointer addresses, cycle conflict info, fi command accepts assembly syntax (for example “fi trap #0”). It is still allowed if configured using Input panel and it was mapped to left/right/up/down events (not horiz/vert). Do not allow opposite joystick directions at the same time (some games crash.) if mapped using Game Ports panel.Saving config file: Confirm overwrite if existing file is read-only.ALT+Space does not anymore open WinUAE window standard menu when input is captured.Previously DISPLAYCHAIN was always forced. Recent Picasso96 multimonitor support: usegfx Picasso96 DISPLAYCHAIN is now only forced if uaegfx monitor is monitor id=0 (shared with native chipset).x86 bridgeboard emulation updated to PCem v17 x86 core.
#WINALIGN 9.0 CD UPDATE#
JIT update (Aranym) + shift instruction flag fix. Prelude A1200 clockport expander support. GVP A1230 Turbo+ Jaws (68030 accelerator). Combitec HD 20 A/HD 40 A (OMTI HD controller). Hardital Synthesis (SCSI HD controller). (S3Trio and S3Virge chipset emulation from PCem) CyberVision 64, CyberVision 64/3D and S3 Virge PCI emulation. Audio internal timing is now accurate, for example low audio period (lower than DMA can support) interrupt and sample reload timing is now cycle-accurate. Also OCS Denise blanking bug on first and last line is now emulated and visible. Can see everything in emulation that real chipset can output in PAL/NTSC compatible modes with adjusted blanking timing when using converters like OSSC. Overscan+ and Extreme display size options. Overrun can be used to create special modes that are still fully PAL (or NTSC) compatible without usual restrictions (for example it is possible to have full overscan, horizontal scrolling in 64-bit fetch mode and still have most sprites available) Bitplane DMA overrun condition is not a special case anymore, all overrun conditions are now fully supported, including bitplane wrap around. 
Multiple DIWSTRT/STOP regions in single scanline supported, including start/stop horizontal wrap around. Vertical is also from vsync to vsync, for example last visible line of display can be line 0 (or even larger if special programmed mode) which wasn’t fully emulated previously.
Display emulation is now from hsync to hsync (not scanline to scanline) which enables accurate emulation of left (programmed modes or blanking modified) and right border (normally visible, position where horizontal position wraps around) edge cases without extra hacks, both bitplanes and sprites. Chipset edge-cases and chipset version specific undocumented behavior emulation improved, for example Copper waiting for Blitter chipset bug is accurately emulated (which causes visible glitches and was not emulated previously), borderblank glitch if horizontal window is opened early. Blitter internal logic emulation updates, for example blitter register modifications when blitter is active are now accurately emulated, line mode with B channel enabled undocumented behavior emulated and more. 
Programmed display mode support greatly improved, for example cycle accurate horizontal blanking (even if it is changed mid-screen), badly documented BEAMCON0 bit combinations accurately emulated, previously unknown undocumented features emulated and more. Agnus/Alice internal DMA cycle processing and RGA bus pipelining (bitplanes, copper, blitter etc) accurately emulated. Major update: custom chipset emulation rewrite (biggest reason for far too long release cycle)
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